Effectiveness of Compiler-Directed Prefetching on Data Mining Benchmarks

For today's increasingly power-constrained multicore systems, integrating simpler and more energy-e±cient in-order cores becomes attractive. However, since in-order processors lack complex hardware support for tolerating long-latency memory accesses, developing compiler technologies to hide such latencies becomes critical. Compiler-directed prefetching has been demonstrated e®ective on some applications. On the application side, a large class of data centric applications has emerged to explore the underlying properties of the explosively growing data. These applications, in contrast to traditional benchmarks, are characterized by substantial thread-level parallelism, complex and unpredictable control °ow, as well as intensive and irregular memory access patterns. These applications are expected to be the dominating workloads on future microprocessors. Thus, in this paper, we investigated the e®ectiveness of compiler-directed prefetching on data mining applications in in-order multicore systems. Our study reveals that although properly inserted prefetch instructions can often e®ectively reduce memory access latencies for data mining applications, the compiler is not always able to exploit this potential. Compiler-directed prefetching can become ine±cient in the presence of complex control °ow and memory access patterns; and architecture dependent behaviors. The integration of multithreaded execution onto a single die makes it even more di±cult for the compiler to insert prefetch instructions, since optimizations that are e®ective for single-threaded execution may or may not be e®ective in multithreaded execution. Thus, compiler-directed prefetching must be judiciously deployed to avoid creating performance bottlenecks that